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A list of all the posts and pages found on the site. For you robots out there is an XML version available for digesting as well.
Pages
Stefan Nikolić
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Posts
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Blog Post number 4
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Blog Post number 2
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Blog Post number 1
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portfolio
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publications
Finding a Needle in the Haystack of Hardened Interconnect Patterns
Stefan Nikolić, Grace Zgheib, and Paolo Ienne
Published in FPL'19 (short paper), 2019
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing
Stefan Nikolić, Grace Zgheib, and Paolo Ienne
Published in FPGA'20, 2020
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths
Stefan Nikolić, Grace Zgheib, and Paolo Ienne
Published in FPL'20 (Best Paper Award), 2020
Global Is the New Local: FPGA Architecture at 5nm and Beyond
Stefan Nikolić, Francky Catthoor, Zsolt Tőkei, and Paolo Ienne
Published in FPGA'21, 2021
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs
Morten B. Petersen, Stefan Nikolić, and Mirjana Stojilović
Published in FPGA'21, 2021
Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence
Stefan Nikolić and Paolo Ienne
Published in FPL'21 (Best Paper Award), 2021
Detailed Placement for Dedicated LUT-Level FPGA Interconnect
Stefan Nikolić, Grace Zgheib, and Paolo Ienne
Published in TRETS, 2022
Regularity Matters: Designing Practical FPGA Switch-Blocks
Stefan Nikolić and Paolo Ienne
Published in FPGA'23, 2023
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck
Shashwat Shrivastava, Stefan Nikolić, Chirag Ravishankar, Dinesh Gaitonde, and Mirjana Stojilović
Published in ICCAD'23, 2023
This paper proposes a new routing algorithm for AMD FPGAs, which turns one of their architectural features—an extremely sparse logic block input interconnect structure—from a major source of routing runtime expenditure into an advantage that allows straightforward parallelization. However, the main advantage is brought by the overal reduction in the amount of work that the router has to do. This reduction is further increased by a simple architectural modification inspired by the new algorithm. The paper was a result of a collaboration with Chirag Ravishankar and Dinesh Gaitonde, which also allowed the experiments to be conducted in a very realistic setting. Read more
Exploring FPGA Switch-Blocks without Explicit Pattern Listing
Stefan Nikolić and Paolo Ienne
Published in TRETS, 2024
Runtime efficient multi-stage router flow for circuit designs
Dinesh Gaitonde, Chirag Ravishankar, and Stefan Nikolić
Published in US Patent Application No. US20240202423A1 (Published, pending approval), 2024
talks
Talk 1 on Relevant Topic in Your Field
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Conference Proceeding talk 3 on Relevant Topic in Your Field
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teaching
Teaching experience 1
Undergraduate course, University 1, Department, 2014
This is a description of a teaching experience. You can use markdown like any other post. Read more
Teaching experience 2
Workshop, University 1, Department, 2015
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