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Posts
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portfolio
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publications
Finding a Needle in the Haystack of Hardened Interconnect Patterns
Stefan Nikolić, Grace Zgheib, and Paolo Ienne
Published in FPL'19 (short paper), 2019
Recommended citation: Stefan Nikolić, Grace Zgheib, and Paolo Ienne. "Finding a Needle in the Haystack of Hardened Interconnect Patterns". In Proceedings of the 29th International Conference on Field Programmable Logic and Applications (FPL), pages 31–37, 9 2019
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Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing
Stefan Nikolić, Grace Zgheib, and Paolo Ienne
Published in FPGA'20, 2020
Recommended citation: Stefan Nikolić, Grace Zgheib, and Paolo Ienne. "Straight to the point: Intra- and intercluster LUT connections to mitigate the delay of programmable routing". In Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 150–60, 2 2020
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Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths
Stefan Nikolić, Grace Zgheib, and Paolo Ienne
Published in FPL'20 (Best Paper Award), 2020
Recommended citation: Stefan Nikolić, Grace Zgheib, and Paolo Ienne. "Timing-driven placement for FPGA architectures with dedicated routing paths". In Proceedings of the 30th International Conference on Field-Programmable Logic and Applications (FPL), pages 153–61, 8 2020
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Global Is the New Local: FPGA Architecture at 5nm and Beyond
Stefan Nikolić, Francky Catthoor, Zsolt Tőkei, and Paolo Ienne
Published in FPGA'21, 2021
Recommended citation: Stefan Nikolić, Francky Catthoor, Zsolt Tőkei, and Paolo Ienne. "Global is the new local: FPGA architecture at 5nm and beyond". In Proceedings of the 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 34–44, 2021.
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NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs
Morten B. Petersen, Stefan Nikolić, and Mirjana Stojilović
Published in FPGA'21, 2021
Recommended citation: Morten B. Petersen, Stefan Nikolić, and Mirjana Stojilović. "NetCracker: A peek into the routing architecture of Xilinx 7-Series FPGAs". In Proceedings of the 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 11–22, 2 2021
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Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence
Stefan Nikolić and Paolo Ienne
Published in FPL'21 (Best Paper Award), 2021
Recommended citation: Stefan Nikolić and Paolo Ienne. Turning pathfinder upside-down: Exploring FPGA switch-blocks by negotiating switch presence. In Proceedings of the 31st International Conference on Field-Programmable Logic and Applications (FPL), pages 225–33, 9 2021
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Detailed Placement for Dedicated LUT-Level FPGA Interconnect
Stefan Nikolić, Grace Zgheib, and Paolo Ienne
Published in TRETS, 2022
Recommended citation: Stefan Nikolić, Grace Zgheib, and Paolo Ienne. "Detailed placement for dedicated LUT-level FPGA interconnect". ACM Trans. Reconfigurable Technol. Syst., 15(4), 12 2022
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Regularity Matters: Designing Practical FPGA Switch-Blocks
Stefan Nikolić and Paolo Ienne
Published in FPGA'23, 2023
Recommended citation: Stefan Nikolić and Paolo Ienne. "Regularity matters: Designing practical FPGA switch-blocks". In Proceedings of the 2023 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2 2023
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IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck
Shashwat Shrivastava, Stefan Nikolić, Chirag Ravishankar, Dinesh Gaitonde, and Mirjana Stojilović
Published in ICCAD'23, 2023
Recommended citation: Shashwat Shrivastava, Stefan Nikolić, Chirag Ravishankar, Dinesh Gaitonde, and Mirjana Stojilović. "IIBLAST: Speeding up commercial FPGA routing by decoupling and mitigating the intra-CLB bottleneck". In Proceedings of the 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 11 2023
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Exploring FPGA Switch-Blocks without Explicit Pattern Listing
Stefan Nikolić and Paolo Ienne
Published in TRETS, 2024
Recommended citation: Stefan Nikolić and Paolo Ienne. "Exploring FPGA switch-blocks without explicit pattern listing". ACM Trans. Reconfigurable Technol. Syst., 17(1), 2 2024
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Runtime efficient multi-stage router flow for circuit designs
Dinesh Gaitonde, Chirag Ravishankar, and Stefan Nikolić
Published in US Patent Application No. US20240202423A1 (Published, pending approval), 2024
Recommended citation: Dinesh Gaitonde, Chirag Ravishankar, and Stefan Nikolić. "Runtime efficient multi-stage router flow for circuit designs", 2024. (patent application no. US 20240202423 A1; published, pending approval)
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Modern Programmable Interconnect Design
Stefan Nikolić
Published in Springer Nature Switzerland AG, 2025
Preface: With Moore’s law coming to an end, today’s rising demand for compute puts increasingly more hope in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experience problems caused by technology scaling. In fact, due to their lower logic density and the need to provide interconnect programmability, rising wire resistance impacts the performance of FPGAs particularly negatively. This is further complicated by the traditional problem of reconfigurable architecture design: exact critical paths are not known at fabrication time.
Recommended citation: Stefan Nikolić, "Modern Programmable Interconnect Design". Springer Nature Switzerland AG, 2025. ISBN: 978-3-031-80628-5
Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox
Shashwat Shrivastava, Stefan Nikolić, Sun Tanaka, Chirag Ravishankar, Dinesh Gaitonde, and Mirjana Stojilović
Published in FCCM'25 (Best Paper Award), 2025
Recommended citation: Shashwat Shrivastava, Stefan Nikolić, Sun Tanaka, Chirag Ravishankar, Dinesh Gaitonde, and Mirjana Stojilović. "Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox"In Proceedings of the 2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 05 2025
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talks
Automating Design of FPGA Switch-Blocks
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This was a research talk hosted by professors André DeHon and Jing Li and their students. Slides
Algorithms for Automated FPGA Interconnect Design
Published:
Abstract Field-Programmable Gate Arrays (FPGAs) are the most popular platform for reconfigurable computing. As such, they provide an appealing way to implement custom hardware, especially for acceleraing rapidly evolving tasks like those found in machine learning inference. Despite being around for almost four decades, there are still many unknowns in designing the FPGA architectures themselves; this is paricularly tue for their programmable interconnect.
Automating the Design of Programmable Interconnect for Reconfigurable Architectures
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This was a short presentation of my thesis at the official Patrick Denantes Award ceremony. Slides
Securing a Bright Future for FPGAs
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Abstract Four years ago, when the news of AMD acquiring Xilinx first became public, FPGAs were a rather hot topic. New reconfigurable chips being rolled out in the back-then latest fabrication technologies were promising such things as dramatic performance boosts in AI inference and fundamentally more secure hardware. Yet, in the second quarter of 2024, AMD reported a 41% drop in year over year revenue of its embedded division into which Xilinx was incorporated. This is in stark contrast with GPUs which were part of similar AI-related promises. Two major reasons for deflated expectations from FPGAs are 1) that FPGAs failed to transition to newer technology nodes in the four years that have passed, thus losing much of the competitive edge that they used to have for most of the XXI century and 2) that attempting to use an FPGA can still be a frustrating experience for domain experts.
Kako radi računar?
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Apstrakt Bez obzira na struku kojoj pripadamo ili naučnu oblast kojom se bavimo, danas svi koristimo računar; ako ništa drugo, onda bar da bismo došli do informacija poput najave ovog predavanja. No, da li vas je ikad zanimalo kako računar zapravo radi? Polazeći od jednog matematičkog problema koji je 1769. formulisao Leonard Ojler, a koji je rešen tek 1966, upotrebom računara, na ovom predavanju ćemo uz minimalne pretpostavke zajedno konstruisati fon Nojmanov računar koji predstavlja osnovu gotovo svih savremenih računara. Pored interaktivnog dela predavanja u kom ćemo naučiti kako računar zaista radi, osvrnućemo se i na neke zanimljive trenutke iz istorije razvoja računarstva u svetu i kod nas. Ako ste se pitali šta će budućim hemičarima, fizičarima i matematičarima informatika, verovatno će vam biti zanimljivo da čujete kako su upravo hemičari, fizičari i matematičari pomogli da računarstvo uopšte postane naučna oblast. Usput ćemo saznati i kakva je veza između jednog sela iz doline Jadra i prvog računara u Jugoslaviji, a nema nikakve veze sa litijumom.
teaching
Teaching experience 1
Undergraduate course, University 1, Department, 2014
This is a description of a teaching experience. You can use markdown like any other post.
Teaching experience 2
Workshop, University 1, Department, 2015
This is a description of a teaching experience. You can use markdown like any other post.