IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck
Shashwat Shrivastava, Stefan Nikolić, Chirag Ravishankar, Dinesh Gaitonde, and Mirjana Stojilović
Published in ICCAD'23, 2023
This paper proposes a new routing algorithm for AMD FPGAs, which turns one of their architectural features—an extremely sparse logic block input interconnect structure—from a major source of routing runtime expenditure into an advantage that allows straightforward parallelization. However, the main advantage is brought by the overal reduction in the amount of work that the router has to do. This reduction is further increased by a simple architectural modification inspired by the new algorithm. The paper was a result of a collaboration with Chirag Ravishankar and Dinesh Gaitonde, which also allowed the experiments to be conducted in a very realistic setting. Read more